system verilog - Parametrized uvm_events for uvm_sequence -

system verilog - Parametrized uvm_events for uvm_sequence -

in verification environment, have mutual sequences set reusability:

class common_sequence(type t = uvm_sequence) extends uvm_sequence#(uvm_sequence_item); `uvm_object_param_utils(common_sequence_t#(t)) function new(string name="common_sequence"); super.new(name); endfunction t sequence; virtual task body(); `uvm_do(sequence); endtask endclass

i create similar can pass in event.

class common_sequence_with_event(type t = uvm_sequence, type e = uvm_event) extends uvm_sequence#(uvm_sequence_item); `uvm_object_param_utils(common_sequence_t#(t,e)) function new(string name="common_sequence"); super.new(name); endfunction t sequence; e event; virtual task body(); event.wait_trigger(); `uvm_do(sequence); endtask endclass

i set event test follows:

class my_test extends uvm_test; `uvm_component_utils(my_test) uvm_event my_event; function new(string name = "my_test", uvm_component parent=null); super.new(name,parent); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); uvm_event my_event = new ("my_event"); endfunction virtual function void end_of_elaboration_phase(uvm_phase phase); super.end_of_elaboration_phase(phase); // schedule sequences sequencers uvm_config_db#(uvm_object_wrapper)::set(this, "env.my_agent.sequencer.reset_phase", "default_sequence", common_sequence#(reset_sequence)::get_type()); uvm_config_db#(uvm_object_wrapper)::set(this, "env.my_agent.sequencer.main_phase", "default_sequence", common_sequence_with_event#(my_sequence, my_event )::get_type()); endfunction endclass

i compilation error: class specialization parameter must constant common_sequence_with_event#(my_sequence, my_event) line.

i guess means parameters passed classes must constant. so, in case, why take reset_sequence passed in parameter.

also, there improve way want achieve?

type parameters must passed types. my_event variable, not type. did not show declarations my_sequence or reset_sequence, assuming class types. need parameter e? won't uvm_event?

system-verilog uvm