counter - DRDY signal in Verilog -

counter - DRDY signal in Verilog -

in recent cpld design implemented frequency counter spi slave interface. spi master mcu reads out counter after signalled drdy pin. counter updates drdy signal flipping (drdy <=~drdy) requires both edges pin interrupt sensitivity @ mcu side. i'd implement more universally, typical adc chip info ready signal behaviour, is: rising edge, held x clocks falling edge. thought should easy stucked in conditional loops beginner in verilog.

here code far:

module ec2(inp, rst, sr, drdy, drdy2, drdy3); input inp, rst, sr; output reg drdy2, drdy3;//leds verification/testing purposes output reg drdy; reg [23:0] q; event data_ready; @(posedge inp or negedge rst) begin if(!rst) begin q <= 24'd0; end else if( (q == 24'd1000000 && sr) || (q == 24'd500000 && !sr)) begin q <= 24'd0; ->data_ready; drdy2 <=~drdy2; end else begin q <= q + 1; end end @(data_ready) begin drdy=1'b1; //wait 10ms? drdy=1'b0; drdy3 = drdy2; end endmodule

events not synthesizable, should convert data_ready signal (reg). sec counter triggers drdy @ data_ready assertion trick:

always @(posedge inp or negedge rst) begin if (rst) begin drdy <= 1'b0; drdy_count <= 4'd0; end else begin if (~drdy && data_ready) begin drdy <= 1'b1; drdy_count <= 4'd0; end else if (drdy) begin drdy_count <= drdy_count + 1; if (drdy_count == 15) drdy <= 1'b0; end end end

counter verilog