Getting warning error in vhdl code -

Getting warning error in vhdl code -

i maintain getting unusual error in code, compiles fine maintain getting warning:

warning: unconnected, internal signal \s(0)d\ promoted input pin.

warning: unconnected, internal signal \s(1)d\ promoted input pin.

the code basic register resets, shifts left , inserts s_in, , loads values set register using pload. can help me figure out wrong it?

library ieee; utilize ieee.std_logic_1164.all; entity special_register port( data: in std_logic_vector(3 downto 0); reset: in std_logic; pload: in std_logic; s_right: in std_logic; s_in: in std_logic; clock : in std_logic; s: in std_logic_vector(1 downto 0); d: out std_logic_vector(3 downto 0); q : out std_logic_vector(3 downto 0)); end special_register; architecture behav of special_register begin process(clock, data, reset, s_in, s, s_right, pload) begin if rising_edge(clock) s(0) <= (s_right); s(1) <= (pload); if (s(1) = '1') d(3) <= data(3); d(2) <= data(2); d(1) <= data(1); d(0) <= data(0); else if (s(0) = '0') d(0) <= q(1); d(1) <= q(2); d(2) <= q(3); d(3) <= s_in; end if; end if; end if; end process; q(3) <= (not reset) , d(3); q(2) <= (not reset) , d(2); q(1) <= (not reset) , d(1); q(0) <= (not reset) , d(0); end behav;

in add-on brian's reply note design specification not vhdl compliant , presumed synthesis tool isn't either:

ghdl -a special_register.vhdl special_register.vhdl:21:2: port "s" can't assigned special_register.vhdl:22:2: port "s" can't assigned special_register.vhdl:29:14: port "q" cannot read special_register.vhdl:30:14: port "q" cannot read special_register.vhdl:31:14: port "q" cannot read special_register.vhdl:37:26: port "d" cannot read special_register.vhdl:38:26: port "d" cannot read special_register.vhdl:39:26: port "d" cannot read special_register.vhdl:40:26: port "d" cannot read ghdl: compilation error

(it seem trying read output port well).

warnings vhdl