linux - Is there a way to identify the instruction that caused the most recent Last Level Cache miss on modern Intel processors? -

linux - Is there a way to identify the instruction that caused the most recent Last Level Cache miss on modern Intel processors? -

i able read hardware counters on lastly level cache misses , references user space using wrmsr select them , rdpmc read them.

however, while of misses obvious references not nail cache, others much more subtle , move around when same code path executed multiple times (order 100,000 times).

i suspect of misses due hardware prefetching, disabled hardware prefetcher through bios, still getting sliding cache misses causes hard pin down.

is there capability in either linux kernel or intel's registers determine address of instruction caused recent lastly level cache miss?

if useful, running 2.6.32-279.el6.x86_64 on intel xeon x3470.

linux performance caching intel msr