Verilog FIFO code written with different styles..one not working and another not working.Can someone explain -

Verilog FIFO code written with different styles..one not working and another not working.Can someone explain -

i have written verilog code fifo using fillcount check means checking if total or empty. there 2 versions of same code. 1 wherei have seprate always block reading,writing,empty /full ,fillcount,and 1 incrementing pointers.this works fine,i have tested , works fine.

module fifo (clk, reset, data_in, put, get, data_out, fillcount, empty, full); parameter depthp2 = 8 ; parameter width = 8 ; input [width-1:0] data_in; input put, get, reset, clk; output fillcount; output reg [width-1:0] data_out; output reg empty, full; reg [3:0]fillcount ; reg [width-1:0] fifo_1[0:depthp2-1]; reg [2:0] rp,wp; always@(posedge clk or posedge reset) begin if( reset ) begin wp <= 0; rp <= 0; end else begin if( !full && set ) wp <= wp + 1; else wp <= wp; if( !empty && ) rp <= rp + 1; else rp <= rp; end end @(fillcount) begin if(fillcount==0) empty =1 ; else empty=0; if(fillcount==8) full=1; else full=0; end @(posedge clk or posedge reset) begin if( reset ) fillcount <= 0; else if( (!full && put) && ( !empty && ) ) fillcount <= fillcount; else if( !full && set ) fillcount <= fillcount + 1; else if( !empty && ) fillcount <= fillcount - 1; else fillcount <= fillcount; end @( posedge clk or posedge reset) begin:reading if( reset ) data_out <= 0; else begin if( && !empty ) data_out <= fifo_1[rp]; else data_out <= data_out; end end @(posedge clk) begin:writing if( set && !full ) fifo_1[ wp ] <= data_in; else fifo_1[ wp ] <= fifo_1[ wp ]; end endmodule

another way had combined few blocks effectng logic(in understanding!!)but not work case when seek read info after writing immediately.it passes other test cases.

i not sure went wrong.. great if point going wrong.

//the code not working always@(posedge clk or posedge reset) begin:writing if(reset) wp<=0; else if( set && !full) begin fifo1[wp]<=data_in; wp<=wp+1; end else begin fifo1[wp]<=fifo1[wp]; wp<=wp; end end always@(posedge clk or posedge reset) begin:reading if(reset) begin rp<=0; data_out<=0; end else if(get && !empty) begin data_out<=fifo1[rp]; rp<=rp+1; end else begin fifo1[rp]<=fifo1[rp]; rp<=rp; end end always@(posedge clk or posedge reset) begin:fillcount if(reset) fillcount<=0; else if((!full && set ) && ( !empty && get)) fillcount<=fillcount; else if(!full && put) fillcount<=fillcount+1; else if(!empty && get) fillcount<=fillcount-1; else fillcount<=fillcount; end always@(fillcount) begin full=(fillcount==8); empty=(fillcount==0); end endmodule

another question : general way of coding in verilog far have learned utilize fsm draw state diagram , utilize them..but had hard time when seek code memory element fifo,tcam or double clock fifo. there approach or way coding these elements .

sorry long question

in "reading" process inadvertantly writing fifo memory:

fifo1[rp]<=fifo1[rp];

if rid of looks things should work okay.

as side note, in sequential process don't need explicitly set values aren't changing.

for example, if take process of yours:

always@(posedge clk or posedge reset) begin:writing if(reset) wp<=0; else if( set && !full) begin fifo1[wp]<=data_in; wp<=wp+1; end else begin fifo1[wp]<=fifo1[wp]; wp<=wp; end end

you can rewrite as:

always@(posedge clk or posedge reset) begin:writing if(reset) wp<=0; else if( set && !full) begin fifo1[wp]<=data_in; wp<=wp+1; end end

and exact same behavior in sim , same hardware when synthesize. implying registers in code , maintain state unless explicitly changed.

verilog fifo vlsi