verilog - Good Counter Design or Possible Metastability Issues? -

verilog - Good Counter Design or Possible Metastability Issues? -

quick summary of goal: design counter triggered variable length auto-reload timer.

a little more verbose: there register value changes (predictably changes, , latched before en signal autoreloadtimer module) sets rate @ counter increments.

here's auto-reload timer:

module autoreloadtimer( clk, rst, en, d, done ); input clk; input rst; input en; input [width-1:0] d; output done; parameter width = 8; // oneshot en -> load wire load; oneshotd oneshot_d( .clk( clk ), .rst( rst ), .in( en ), .re( load ) ); reg [width-1:0] counter, load_value; @( posedge clk ) begin if ( rst ) begin counter <= {width{1'b1}}; load_value <= {width{1'b1}}; end else if ( load ) begin counter <= d; load_value <= d; end else if (counter == 0 ) begin counter <= load_value; load_value <= load_value; end else begin counter <= counter - 1'b1; load_value <= load_value; end end assign done = ( counter == 0 ); endmodule

and here counter triggered done signal autoreloadtimer module:

module counter( clk, rst, en, clr, q ); input clk; input rst; input en; input clr; output [width-1:0] q; parameter width = 8; reg [width-1:0] ctr; @( posedge clk ) begin if ( rst ) begin ctr <= {width{1'b0}}; end else if ( clr ) begin ctr <= {width{1'b0}}; end else if ( en ) begin ctr <= ctr + 1'b1; end else begin ctr <= ctr; end end assign q = ctr; endmodule

and here portion of waveform testbench:

what i'm curious here counter's stability - issue done signal goes low @ rising border of clock? i'm still new verilog , digital design. i'm familiar term , thought of metastability i'm not comfortable understanding of it.

looking input, criticism, etc.

edit forgot include configuration had modules in produce diagram:

wire art_done; autoreloadtimer art0 ( .clk( clk ), .rst( rst ), .en( en ), .d( 4 ), .done( art_done ) ); counter uut ( .clk(clk), .rst(rst), .en(art_done), .clr(clr), .q(q) );

as long autoreloadtimer , counter modules, logic uses done signal on same clock, won't have metastability issues. have synchronous implementation. naturally, must meet timing requirements of device using

the done signal alter little combinatorial path delay after rising clock border causes counter nail 0. logic uses done signal has rest of clock period before next rising edge, needs (more combinatorial logic) , still meet setup time of register input conditioned done signal.

the metastability issues arise if input registers transitioning right clock transitioning. can happen if info that's beingness registered coming register uses asynchronous clock, or if register's setup or hold timing violated.

counter verilog