c++ - Preventing or blocking cpu data cache loading -

c++ - Preventing or blocking cpu data cache loading -

i'm tasked evaluating various flavors of arm processors (benchmarking), scheme on chip (soc). soc's have lot of info cache, others have little. because of this, i'd programme block info cache.

i have written walking 1 test accesses memory outside core, on soc. i'm going run on our nowadays processor, has little info cache, , run on cortex m3 processor, has lot of info cache memory.

i'm focusing on durations fetch memory outside processor. if set size of memory walking 1 size larger info cache, run test "exponentiates" in time. example, little size of memory, test runs in minutes, larger memory sizes, test takes hours.

question: there idiom can used prevent processor loading entire array processor's info cache? (note: tagged c , c++ because have alternative take between languages. if c has no idiom, c++ does, seek c++ first.)

platform: various embedded or scheme on chip (development / evaluation boards), no os. processor: arm cortex series different peripherals on chip , different info cache sizes. compilers: iar embedded workbench, gnu c, gnu c++ (used in background various board suppliers).

unless compiler provides functions access memory part protection registers, you'll need assembly set memory region(s) non-cacheable:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/chdhdahb.html

or mentioned below globally disable level 1 info , instruction cache via bits 2 , 12 of c1 command register, accessed via co-processor register 15 = cp 15:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0338g/babebdcb.html

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0338g/babgdhif.html

this assumes arm processors have cp 15 functionality. there may other command registers might useful tests. i'm not sure how done on arm processors without cp 15 functionality.

c++ c arm benchmarking cpu-cache