verilog - Syntax error near "posedge" -

verilog - Syntax error near "posedge" -

i'm trying create alter state @ every posedge of clk , posedge of sclk , compiler throwing error @ posedge.

module spi(output mosi, input miso, input dbus, input sclk,input cs, input clk, input rst_b); reg [1:0] state; reg [1:0] next_state; else if (posedge clk && posedge sclk) begin state <= next_state; if(clr == 0) count <= 0; else if(inc == 1) count <= count +1;

there's couple things wrong this. firstly, why using 2 clocks "clk" , "sclk" , anding them together? utilize one. secondly, should within always block. don't utilize posedge if statement.

e.g.

always @ (posedge clk) begin // stuff

verilog