scala - Chisel synchronous read memory -

scala - Chisel synchronous read memory -

i'm trying generate verilog memory synchronous read next chisel

val my_mem = mem(bits(width=64), 4096, seqread=true) val read_data = reg(bits(width=64)) when(io.re) { read_data := my_mem(io.addr) } io.ret_data := read_data

however, generates verilog this

wire[63:0] t1; reg [63:0] read_data; assign t1 = my_mem[io_addr]; @(posedge clk) begin if(io_re) begin read_data <= t1; end

what doing wrong chisel generate verilog has memory read within block?

the chisel manual state proper way create synchronous memory register address, not read data. although unintuitive, register re-timing, conceptually same thing.

val my_mem = mem(bits(width=64), 4096, seqread=true) val reg_raddr = reg(uint()) val rdata = my_mem(reg_raddr) when (io.re) { reg_raddr := io.addr }

which generates this:

assign io_out = t0; assign t0 = my_mem[reg_raddr]; @(posedge clk) begin if(io_re) begin reg_raddr <= io_addr; end end

the info read not in block, don't believe necessary synthesis tools pick want synchronous memory.

scala chisel