Entries for Subprograms in VHDL -

Entries for Subprograms in VHDL -

i have 2 functions in code :

function derivative(error, previous_error, dt :in std_logic_vector(7 downto 0)) homecoming std_logic_vector variable derivative_val: std_logic_vector(15 downto 0); begin derivative_val := div(sub(error,previous_error),dt); homecoming derivative_val; end derivative; function mul(num1,num2 : in std_logic_vector(7 downto 0)) homecoming std_logic_vector variable v_test_variable1 : integer; variable v_test_variable2 : integer; variable n_times: integer:=1; variable product: integer:=0; begin v_test_variable1 := to_integer(unsigned(num1)) ; v_test_variable2 := to_integer(unsigned(num2)) ; n_times in 1 v_test_variable2 loop product:=product + v_test_variable1; end loop; homecoming std_logic_vector(to_unsigned(product,16)); end mul;

in later half trying assign variable.

variable derivative_term: std_logic_vector(15 downto 0) := x"0000"; derivative_term := mul(mul(kp,td), derivative(error, previous_error,dt));

on compilation, getting :

no feasible entries subprogram "mul".

is there other way utilize it? in advance.

the mul function takes arguments num* type std_logic_vector(7 downto 0) length 8, , returns result type std_logic_vector of length 16.

so when calling mul(mul(...), ...) outer mul gets first argument length 16 of type std_logic_vector, not match required argument length function.

instead of writing own multiplication function, utilize "*" ieee.numeric_std, can used as:

slv_16_0 <= std_logic_vector(unsigned(slv_8_0) * unsigned(slv_8_1));

it handles unknown values, 'x', , resulting length sum of length 2 arguments.

vhdl